EDUCATION_________________________________________

University of Illinois, Urbana - Champaign, IL Jan 2006 - Present PhD candidate in Computer Engineering, ECE Dept. Involved in Computer-Aided-Design and Computer-Architecture research work

Imperial College (Univ. of London), London, UK 1999 - 2000 MSc in "Analogue and Digital Integrated Circuit Design", EEE Dept. Thesis on "Implementations of Units for Floating Point Arithmetic"

University of Patras, Patras, Greece 1994 - 1999 MEng in Electrical & Computer Engineering Dept. Thesis on "VLSI Implementation of Data Encryption Algorithms"

RESEARCH & TEACHING EXPERIENCE________________________________________

University of Illinois, Urbana - Champaign, IL Jan 2006 - Present - Research Assistant at Coordinated Science Laboratory involved in projects related to: - High-level synthesis for multi-core accelerators, under Prof. D. Chen - GPU parallel programming models in heterogeneous parallel processors, under Prof. W-M. Hwu - Memory consistency and cache coherence for chip multiprocessors, under Prof. R. Kumar

- Teaching Assistant - Newly introduced graduate course ECE598BL on "Design & Synthesis for SOC" Fall '06, Fall '07 - Senior level undergrad laboratory on Microcomputers (ECE412) Spring '08

- Mentor for Intel Scholar Undergraduate Research (ISUR) program 2007 - 2009 - Program for promoting undergraduate research among women and minority engineering students

WORK EXPERIENCE________________________________________

Advanced Micro Devices (AMD), Austin, TX Summer 2007 - Co-Op Engineer in micro-processor design and verification site - Worked in the verification of a low-power mobile multi-core processor for laptops

ATMEL, Patras, Greece 2004 - 2005 - Member of the ASIC group involved in SoC design and implementation - Involved in the design of complex heterogeneous multi-processor communication ICs

Infineon Technologies, Bristol, UK 2000 - 2003 - Member of micro-processor team designing Infineon's TriCore2 (TC2) embedded processor. - Lead designer of TriCore2 memory management and load-store pipeline unit - Co - designer of TriCore2 integer pipeline unit - Involved in the synthesis and physical implementation of TriCore2

Eesti Veev�rk, Tallinn, Estonia Summer 1998 - Summer intern, worked on the design and implementation of the company's web site

Ajuntament de Girona, Girona, Spain Summer 1997 - Summer intern, developed a Geographical Information System (GIS) application in Visual Basic

AWARDS____________________________________________

Symposium on Application Specific Processors Best Paper Award, Jul 2009 Design Automation Summer School (DASS) Travel Award, Jul 2009 Design Automation Conference (DAC) Student Booth Travel Award, Jul 2009 Ernest A. Reid Graduate Fellowship Award, Apr 2009 Intel Scholar Undergraduate Research Mentoring Fellowship, 2007 - 2009

ACTIVITIES________________________________________

Student Member, IEEE Student Member, ACM Member, Technical Chamber of Greece President, Hellenic Student Association at UIUC

SKILLS____________________________________________

IC Design: RTL & transistor level design, Simulation, Synthesis, Place & Route Programming: C / C++, SystemC, Tcl, Perl, Visual Basic, Assembly, Fortran Data Management: SQL, Office, Clearcase, CVS, FrontPage, Unix, Linux, MS Windows