Since 1997, he has defined the physical design roadmap for the International Technology Roadmap for Semiconductors (ITRS), and has chaired the U.S. and international working groups for Design technology for the 2001 through 2003 ITRS renewals. In the MARCO GSRC, he initially led the "Fabrics" thrust and has since led the "Calibrating Achievable Design" theme. His research is mainly in physical design and performance analysis of VLSI, as well as the VLSI design-manufacturing interface. Other research interests include combinatorial and graph algorithms, and large-scale heuristic global optimization.