CoreConnect Model: A cycle-accurate IBM CoreConnect model using Operation State Machines (OSMs)
Xinping Zhu, 6 Oct 2004
Last updated: 13 Dec 2004

Primary Author: Xinping Zhu (Princeton)

CoreConnect is a complete model tookit which can model and simulate 32-bit IBM CoreConnect Bus Architecture using Operation State Machine (OSM) models.

The concurrency model - the OSM - is based on works by Wei Qin, who developed a fast ARM simulator SimIt-ARM.

The specification we used in this study is based on

1. IBM 32-bit Processor Local Bus Architecture Specification Version 2.9. coreconnect_32bit.pdf
2. PLB Functional Model Toolkit, Chap 6, PLB Bus Functional Language coreconnect_bfl.pdf

The Official IBM CoreConnect Website : http://www-306.ibm.com/chips/products/coreconnect/

Key Features and Highlights

1. A C/C++ written cycle-accurate coreconnect bus model and its corresponding description.
2. A library of reusable communication modules such as timers, arbiters, etc.
3. Fast Simulation Speed. (> 200K cycles per second for a 4 node bus architecture on a P4 with Linux )

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Reference

X.Zhu, W. Qin, S. Malik, Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation , Proceedings of International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Sep, 2004(PDF, Powerpoint)

X.Zhu, S.Malik, "Using A Communication Architecture Specification in an Application-driven Retargetable Prototyping Platform for Distributed Processing", Proceedings of 2004 Design Automation and Test in Europe Conference (DATE 04), Feb, 2004 (PDF )

Wei Qin, Sharad Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. Design, Automation, and Test in Europe (DATE), March, 2003.

W. Qin, Mescal Architecture Description Language 1.0, Draft.