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Allayer Technologies |
C-Port, now Motorola |
EZChip |
IBM |
Intel (Level One) |
Maker, now Conexant |
MMC Networks, now Applied Micro Circuits |
SiTera,
now Vitesse |
Lexra |
Agere, now Lucent |
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ALxxx |
C-5 DCP |
NP-1 |
PowerNP |
IXP1200 |
Traffic Stream Processor |
nP |
PRISM IQ2000 |
NetVortex |
FPP/RSP/ASI |
| Application |
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Capacity |
(e.g. xxGbits/s) |
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5 Gb/s |
10 Gb/s |
8 Gb/s |
2.6 Gb/s |
OC-3 to OC-48 |
5 Gb/s |
6.4 Gb/s |
>10 Gb/s |
5 Gb/s |
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OSI layers |
(e.g. 2-4) |
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2-4 |
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2-7 |
2-5 |
2-7 |
Layer 2 – internetworking
(AAL SAR, MPLS), buffer management, congestion control, bandwidth management,
CRC & FCR error checking, traffic shaping |
2-7 |
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2-4 |
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Physical
support |
(e.g. ATM, frame relay,...) |
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Gigabit Ethernet, SONET |
SONET, ATM, Gigabit Ethernet |
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SONET, Gigabit Etherner |
ATM, SONET, Gigabit Ethernet |
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| Micro-architecture |
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Central
control |
(e.g. RISC for IXP, VLIW) |
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1 executive
processor to coordinate with external processors |
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On-chip
Power PC core; can also connect external control processor |
on-chip
200MHz StrongARM coordinates system activities |
32-bit RISC processor
optimized for traffic stream processing – specialized instructions; efficient
dispatch of parallel hardware operations; context-switching overhead
minimized by background process |
Network-optimized
instruction set, zero-overhead task switching |
none |
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No |
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Multi-PE |
(e.g. IXP mEngine) |
|
ring-of-switches (ROX)
buss architecture supports up to 4 network processors, plus additional
processors that offer switch management |
16 channel
processors |
64 Task
Oriented Processors (TOPs) |
16
programmable protocol processors |
6
programmable microengines with hardware (zero-overhead swapping) context
support for four threads – total of 24 threads |
No |
No |
4 CPUs that
do route processing and system management; Optimized instruction set for
network operations |
modified
RISC with special instructions and threading support |
3 - Fast
Pattern Processor (FPP), Routing Switch Processor (RSP), and Agere System
Interface (ASI) |
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Task-based |
(e.g. hash engine for IXP) |
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· fabric
processor: for using multiple C-5’s in a fabric
· table lookup unit: table lookup and update info
· queue management
· buffer management: fast, flexible memory management |
Each TOP has
a customized instruction set and data path
· Parse: identifies and extracts various packet headers and protocols
· Search: performs lookups at different levels (layer 2-7)
· Resolve: assign packet to appropriate queue and/or
port
· Modify: modifies packet contents
TOP’s in a super-pipelining and superscalar architecture |
each
programmable protocol processor pair shares a hardware coprocessor to
accelerate tree searching and frame manipulation |
in addition
to microengines, specialized functional units for hashing and queue
management |
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network
co-processors that do packet processing for classification, lookups, and
QoS/Cos priority checking |
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- FPP
performs pattern matching on a frame
- RSP performs actions based on FPP results
- ASI takes care of "slow path" processing |
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Reconfigurable |
(e.g. none for IXP) |
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No |
No |
No |
No |
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No |
No |
No |
No |
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Inter-PE communication structure |
(e.g. 2 buses for IXP) |
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each channel
processor can be used individually, organized in a bank to handle a parallel
data stream, or organized serially.
60Gbps bus that connects all channel processors, and co-processors |
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Microengines
communicate via Fast Bus Interface (FBI) |
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Designed to
work with other nP’s, MMC switch chips, nP co-processors |
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64-bit
Vortex bus that runs at chip speed (427 MHz) |
Functional
Bus Interface to connect FPP/ASI |
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| Archictecture |
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# of PC's |
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16 |
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16 |
6 |
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1 |
4 |
2 |
3 |
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# of threads per PC |
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4 |
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2 |
4 |
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5 |
configurable
from 1-4 (soon 1-8) |
64 for the
FPP |
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| Software
Support |
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Compilers |
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C/C++ |
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Assembler only |
Assembler only |
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yes |
yes |
yes |
Interpretation
from Lucent's Functional Programming Language for the FPP |
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Operating systems |
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Libraries |
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C-Ware
Communications Programming Interfaces (CPI) – open set of standard interfaces
that abstract “common network task building blocks” such as physical
interface management, data forwarding, table lookups, buffer management,
queueing operations, etc. The CPI is
used to access the co-processors.
There is also a C-Ware reference library for use in common
applications. |
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none |
none |
PortMaker software
provides a modular software architecture on top of the TSP |
network
software reference library |
Network
software library for common functions |
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| Physical implementation |
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Process technology |
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Die size |
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Core |
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Yes |
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Speed |
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Power |
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7 W |
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| Please
send feedback to Niraj Shah |
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