e-seminar Schedule
Date
Day
Time
Name
Affiliation
Title
11/1/11
Tuesday
12:00 pm EST
Carole-Jean Wu
Princeton
Characterizing and Improving Last-level Cache Management using Signature-based and Prefetch-aware Approaches
09/13/11
Daniel Schwartz-Narbonne
Parallel Assertions for Debugging Parallel Programs
06/21/11
Joseph Sloan
UIUC
Algorithmic Techniques for Fault Tolerance
06/14/11
Yoongu Kim
CMU
Memory Scheduling to Enhance Both System Throughput and Fairness
05/17/11
Margaret Martonosi
Hardware-Software Interface Design Issues for Parallelism and Power-Efficiency
05/10/11
Jason Cong
UCLA
Architecture Support for Customization and Specialization
04/26/11
Deming Chen
Porting Performance across GPUs and FPGAs through Multilevel Granularity Parallelism
04/19/11
Narayanan Sundaram
UC Berkeley
Large Displacement Optical Flow and Video Segmentation on Parallel Platforms
04/05/11
Chenjie Gu
Nonlinear Phase/Timing Macromodeling of Analog/Mixed Signal Circuits
03/15/11
Konstantinos AisoposAndrew DeOrio
MITUniversity of Michigan
Resilient On-Chip Networks for Many-Core Chips
03/04/11
Naresh Shanbhag and Boris Murmann
UIUC Stanford
Joint C2S2/GSRC Workshop on: System and Digitally Assisted Analog-Mixed Signal Design
03/01/11
K.T. Tim Cheng
UC Santa Barbara
Bug Modeling and Coverage Metrics for Post-Silicon Validation
02/01/11
Pierluigi Nuzzo
System-level Design of Analog and Mixed-Signal Circuits Using Contracts and Formal Methods for Constraint Satisfiability Solving
01/25/11
Daniel Sanchez
Stanford University
Flexible Architectural Support for Hardware-Accelerated Fine-Grain Scheduling
01/11/11
Pat Hanrahan
Domain-specific Languages for Heterogeneous Computer Platforms
12/14/10
Todd Austin
University of Michigan
Massively Scalable Security Vulnerability Analysis
12/07/10
Subhasish Mitra
Robust System Design: Overcoming Post-Silicon Validation and Reliability Challenges
11/30/10
Sanjit A. Seshia
Specification Mining for Verification, Diagnosis, and Resilience
11/16/10
Dennis Sylvester
Univ. Of Michigan
Designing for Robustness and Low-Power
10/26/10
Pradeep Ramachandran
SWAT: A Complete Solution for Low-Cost In-Core Fault Resiliency
10/19/10
Doug Carmean
Intel Labs
Perfecting the Mind Meld: Hardware Architecture Optimized for Software
10/12/10
Moinuddin Qureshi
IBM
Scaling the Memory Wall with Phase Change Memories
9/21/10
Abhijit Chatterjee
Georgia Tech
Self-Aware Wireless Communication and Signal Processing Systems: Real-Time Adaptation for Error Resilience, Low Power and Performance
6/29/10
Andrew Kahng
UCSD
Challenges of Estimation and Projection in System Roadmapping
5/20/10
Thursday
Andrew Singer
FCRP - Connectivity Cross-Cut Workshop
5/11/10
Andrew DeOrio
Uni. Of Michigan
What's Wrong With My Multicore? -- Post-silicon validation of the memory subsystem
4/20/10
John Ousterhout
Stanford
RAMCloud: Scalable High-Performance Storage Entirely in DRAM
4/13/10
Rajeev Alur
UPenn
Architecture-aware Analysis of Concurrent Software
3/30/10
Arnab Sinha
Runtime Checking of Serializability in Software Transactional Memory
3/23/10
Onur Mutlu
Designing High-Performance and Fair Shared Multi-core Memory Systems: Two Approaches
3/9/10
Christian Bienia
The PARSEC Benchmark Suite
2/23/10
John O'Leary
Intel
Validation Challenges in Firmware and Low Level Software
2/16/10
David Brooks
Harvard
Architectures for Accelerator-Centric Computing
2/9/10
Emery Berger
UMass
Safe Multithreaded Programming for C/C++
1/26/10
Silvio Savarese
Visual Recognition in the Three-Dimensional World
1/19/10
Naveen Verma
Algorithm Driven Platform Electronics for Embedded Health-Care
12/15/09
Rakesh Kumar
Computing with Stochastic Processors
