Conclusions of the I Workshop on MARCO/GSRC bookshelf

Andrew Caldwell, Andrew Kahng and Igor Markov

Attendees

• Andrew Caldwell, UCLA
• Andrew Kahng, UCLA
• John Lillis, UIC
• Wangning Long, UCLA
• Patrick Madden, SUNY Binghamton
• Igor Markov, UCLA
• Abdallah Tabbara, UCB
• Bassam Tabbara, UCB
• Maogang Wang, Northwestern Univ.
• Linda Wu, UCSC
• Shawn Zhang, UCSC

Talks and discussions

Existing slots and formats were described in presentations by Patrick Madden ( Global Routing), John Lillis ( Single Interconnect Tree Synthesis), Linda Wu/Shawn Zhang ( Block packing), and Andrew Kahng/Andrew Caldwell (Generic Hypergraph entry, Partitioning slot and Placement slot). Most of these formats were discussed in detail as they were presented. Afternoon breakout sessions sought to resolve overlaps and gaps within partitioning, placement and global routing.

Additional Saturday highlights included:

• Christopher Hylands presented the GSRC Software Day materials, in particular, the Reekie/Hylands presentatation on good academic software practices
• Appearances by Jason Cong / Sung-Kyu Lim (start of morning), Dirk Stroobandt (morning, early afternoon), Ashok Jagannathan (dial-in from late morning through evening), and Richard Newton (dial-in in early afternoon)

Workshop Agreements

1. New formats with redundant/duplicated information may be acceptable when existing formats are either overly verbose/redundant for a given tool/flow or when their abstract syntax does not go well with needs of a given tool/flow. In this case, new data formats will provide noew "views" of existing data, and conversion should be explicitely supported.
   • example: .SITSpins in the SITS slot, which captures in a single format what would require .masters, .nodes, .nets (from Fundamental-Hypergraph slot) and .pl (from SCell Placement slot) to otherwise specify
2. We will adopt XML, given the following considerations
   • XML allows formalization of prose and example-based "definitions" that have typically been used
   • XML potentially simplifies parsing tasks and getting to in-memory structures, given standard (and browser-embedded) parsers
   • in practice, formats should remain "fixed", and XML adoption should remain as transparent as possible to existing parsers (for adoptability)
   • other concrete syntax issues were discussed, e.g., case-insensitivity for keywords/tags (case-sensitivity otherwise)
   • XML pointers, tutorials and example formats have now been posted.
3. We agreed on a number of useful "flows" that should be supported by formats and slot entries (solvers, parsers, etc.); if nothing else, these are our first-level sanity-checks:
   • Partition --> BlockPlace --> SCellPlace (shown at December review)
   • SCellPlace --> GRoute --> SCellPlace
   • Groute --> SITS --> GRoute
   • GRoute --> IncrementalSCellPlace --> IncrGRoute
   • Place --> GRoute --> Droute
   • CoarsePlace --> SITS --> DetailedPlace
   • Links to performance analysis

Workshop Achievements

1. New slots/formats defined
   • .perfconstr
     • path timing constraints similar to SDF, with no false path and multicycle semantics for now (easily possible via extensions)
     • both class-to-class (set of output pins, to set of input pins; cf. "stage-based constraints") and explicit path constraint types accomodated
     • both delay and length constraints accomodated
     • noise margin constraints (at all input pins in all paths) accomodated
     • allows elimination of .tcr format (SITS slot) and .etime/.ptime formats (BlockPlacement slot)
     • additionally allows per-net bounds on wirelength or total load capacitance (for both performance, reliability)
   • .spatialconstr
     • absolute and relative spatial constraints, including region constraints, location constraints, grouping constraints
     • replaces previous BlockPlacement formats
   • .timingmodels
     • corresponds to .lib (Synopsys) / .tlf (Cadence) table-based timing model format for gate-level calculation of gate load delay and gate output slew
   • Fundamental/Technology
     • fundamentals of technology, in some sense a "minimal set of technology data" for most layout creation slots
     • multiple layers, viatype, power supplies accomodated
     • for each layer, all RLC (mutual and self) parasitics and inter- and intra-layer dielectric permittivities, as well as physical dimensions, can be specified (a table-based specification of interconnect capacitance values is permitted)
     • for each layer, discrete or continuous wire sizing and spacing options can be specified
     • a simplified buffer/inverter library format is defined which refers to .masters (Fundamental-Hypergraph slot) but then allows continuous or discrete sizing of particular devices, with simple "extrapolations" of on-resistance, input capacitance, area, etc.
2. Refinements of existing slots
   • Fundamental/Hypergraph
     • .masters format allows specification of area/boundary pins and alternative node (block) dimensions, thus allowing unification of SCellPlace and BlockPlace (with elimination of redundant formats)
     • .masters format now specifies unateness, "intrinsic delay", a richer set of pin classes (I/O/IO/CLK/PWR/UNK), etc. -- again, allowing more layout creation tools to perform their tasks with just .masters information (not necessarily .lib/.tlf .timingmodels information, for example)
     • a .masterpins extension for detailed pin geometry has been added
     • .masters and .nodes separation has been enforced, in the sense that .node instances MUST refer to .masters definitions; this recalls standard separations in existing specification formats for hierarchical design (cf. Cadence LEF, DEF). detailed explanations of the adoptability of this change for communities such as the hypergraph partitioning community (i.e., why the overhead is tolerable) have been added to format descriptions
     • DRAFT XML FORMATS for key Fundamental formats are now available for comment (generic hierarchy and .masters in generic hypergraph); we intend to adopt XML as rapidly as possible, e.g., for establishing the Partition/BlockPlace/ SCellPlace mini-flow.
   • Standard Cell Placement
     • a new "coarse placement" use model is supported by use of
     • .blk and .partsol formats; these have been documented
   • Global Routing and SITS
     • .grg costing definitions clarified (STILL NEED TO BE ADDED - PM) as functions of demand/supply, supply, #buffers, buffer area, ...)
     • .topo extended to capture ggrid/congestion map independent specification of global routes, as well as specification of detailed routes: route specification is possible via exact edge embedding, with width, spacing, corridor information added; this allows elimination of the .pmap (SITS slot) format

Open Issues

1. Calculation of Rd in table-based mode (e.g., from .timingmodels table format); need a .res calculator or table generator
2. Use of "database units" for length ("DBU") was attempted, but then dropped. currently we will go with SI units, but probably will require some notion of a manufacturing grid, if not a DBU.
3. Analysis slots, with supporting "calculators", are an imminent black hole
   • ROM, Ceff, gate load delay, wire delay (multi-pin net), path delay (with appropriate 10-90 and 50-50 convention awareness re .timingmodels characterizations), are needed
   • parasitic estimations must soon be added into our generic analysis slot (various levels of accuracy; various information regimes such as grouted, gplaced, drouted, etc.)
   • calculators may eventually be separated (power, timing, noise, reliability) but for now we will establish a single generic analysis slot
4. Power library models (table format and axes similar to .timingmodels) are needed, eventually
5. No semantics available for "obstacles" passed down into placement or routing
6. Semantic consistency checks
7. Units (delays, lengths)